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MAX9880A Evaluation Kit
Enable Register
The Enable register provides enables for the left/right
line inputs, left/right line outputs, and left/right DACs and
ADCs. The line input and output enables are accessed
from Left Line Input and Right Line Input windows and
the line outputs are configurable through the Left Line
Out Enable and Right Line Out Enable windows. Figure
17 shows which GUI blocks provide access to the line
input and line output enables.
The left and right DAC and ADC enables are accessed
by selecting the DAC and ADC blocks available on both
the Analog Audio and Digital Audio tabs. Note that
when enabling the right DAC/ADC, the left DAC/ADC
should also be enabled.
System Shutdown Register
The register’s SHDN bit is used to place the device in a
lower-power shutdown mode. This feature is controlled
by the MAX9880A Power button at the top of the main
software window. This register is also used to configure
the device crystal oscillator. This is configured by select-
ing the CRYSTAL block on the Digital Audio tab.
Device Revision ID
The device’s revision ID is stored in registers 0x14 and
0xFF. After the software has established a connection to
the EV kit and device, it reads one of these two registers
to determine the device’s revision ID. In SPI mode, the
0x214 (0x14 in I 2 C mode) register is read, and in I 2 C
mode the 0xFF register is read. If the revision ID is not
recognized, the software displays a dialog box informing
that a noncompatible device has been detected.
Note: When in SPI mode, the 0xFF register is not
accessible.
Figure 16. Headphone Modes (2 of 8)
Table 11. Jack Detect/Jack Status Controls
GUI CONTROL
Jack Detection radio buttons
Jack Detect Debounce radio buttons
Jack Sense group box
Jack Action group box
Jack Sense Weak Pullup group box
DESCRIPTION
Configures JDTEN bit (enable: JDETEN = 1).
Configures the JDEB bits.
Displays the status of the JACKSNS bits. This requires that Jack Detection be enabled
(JDETEN = 1).
Displays the results of the Jack Detection logic, when JDETEN = 1.
Configures the JDWK bit.
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